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SI5345A-D04313-GMR
+BOMIC JITTER ATTENUATOR/MULTIPLEXER
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メーカースカイワークス・ソリューションズ株式会社
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メーカー品番 #SI5345A-D04313-GMR
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データシート SI5345A-D04313-GMR DataSheet
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パッケージ QFN-64
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在庫状況6667
365 日間品質保証
7*24 日間の品質保証
90-時間単位のサービス保証
1日間のアフターサービス保証
仕様
| 属性 | 値 |
| Package / Case | Tape & Reel (TR) |
| Part Status | Active |
概要
Description
Features
- Flexible jitter-cleaning clock generator with multi-output distribution
- Any-Output, Any-Frequency capability for programmable output clocks
- Internal PLLs/VCO-based frequency synthesis for precise, low-jitter clocks
- I2C (two-wire) control interface for programming frequencies, enables, and drive settings
- Programmable output enables/power-downs and glitch-free frequency switching
- Output clock monitoring and fault detection (loss of signal, out-of-lock indicators)
- Spread-spectrum clocking support to reduce EMI
- Suitable for high-speed SERDES, memory, PCIe, Ethernet, and other timing-critical sources
- RoHS-compliant packaging (GMR) with suitable footprint for dense designs
Note: The D04313-GMR suffix and package code denote lot/date and packaging, not functional differences.
Pinout
- Function: Multi-output clock generator / jitter-cleaning zero-delay buffer (programmable via I2C to synthesize multiple clock outputs from a reference).
Manufacturer
- What kind of company: A fabless semiconductor company that designs and sells mixed-signal ICs, including timing devices (clock generators/zero-delay buffers) and related embedded solutions.
Application
- High‑speed serial interfaces: PCIe, SATA/SAS, USB 3.x, HDMI/DisplayPort
- Networking/telecom equipment: switches, routers, line cards, PHY timing
- Data‑center/servers: CPU/memory/SoC clocks, PCIe and memory clock distribution
- FPGA/ASIC designs needing multiple synchronized clocks and SERDES references
- Consumer electronics and multimedia: video/audio timing
- Test and measurement gear requiring ultra‑low jitter reference clocks